NEO claims 5x denser AI cache and 10x HBM

NEO Semiconductor launched NEO.AI with company claims of 5x higher on-chip memory density from X-SRAM and 10x higher HBM capacity from 3D X-DRAM. Its X-SRAM technical page says a two-transistor cell could raise accelerator SRAM from today’s 200–400 MB range to 1–2 GB, while the platform announcement says 3D X-DRAM has passed proof-of-concept validation but remains on a path toward commercialization. After the HBF tiering standard put 512 GB of flash beside HBM, builders should file NEO.AI as a second attack on the memory wall—promising architecture, not independently benchmarked production silicon.