Tier IV open-sources a Level 4 chip design

Tier IV has joined Japan’s JST semiconductor program to design a software-defined SoC for Level 4 autonomous driving and open-source its chip logic, compiler, and related toolchain. The company’s Aug. 14 announcement says the architecture is meant to run Transformer inference from embedded devices drawing several watts to vehicle controllers using several tens of watts, with TOSA separating models from hardware and formal verification checking selected transformations. Physical-AI teams should watch the project as an open alternative to GPU-bound stacks, alongside the push toward purpose-built AI CPUs, not as shipping silicon yet.